Integrated circuit (IC) chips are typically assembled into packages that are soldered to a printed circuit board (PCB). Each integrated circuit chip may be connected to a substrate of the package with a number of solder bumps in a process commonly referred to as controlled collapsed chip connection (C4).
As known in the art, an interposer substrate such as a silicon interposer with through silicon vias (TSVs) is usually used in semiconductor packaging to “fan out” the contacts of the integrated circuit chips. However, TSV silicon interposers are expensive. Therefore, it is desirable to provide an improved semiconductor package having an interposer without using TSV and silicon substrate (TSV-less interposer), while the interposer is still able to provide very fine pitch interconnections.
However, the RDL interposer structure without TSV is thin and is difficult to handle during the packaging process. For example, a lithographic process is often used to define pad openings for further connection on the interposer. The warping of the thin RDL interposer structure may result in misalignment of the pad opening and hence reducing the production yield. Therefore, it is also desirable to provide a method for fabricating a semiconductor package utilizing such a thin RDL interposer structure, which is capable of overcoming the difficulty as mentioned above.